Wheel speed signal processing circuit for wheel slip control systems

ABSTRACT

A control system for varying the pressure applied to fluidcontrolled brake actuating mechanisms upon detection of both a wheel deceleration in excess of a predetermined threshold and a subsequent incremental decrease in wheel velocity greater than a continuously-varying reference increment Delta v of wheel speed. This reference increment Delta v is inversely related to a variable reference signal which is directly related to the rate of change of wheel speed. Thus, the continuously-varying reference increment of wheel speed Delta v is inversely related to the rate of change of wheel speed. Consequently, the period of time between occurrence of a wheel deceleration in excess of said predetermined threshold and the relief of brake line fluid pressure is shorter when wheel speed decreases rapidly and longer when wheel speed decreases slowly. Compensation is thus made for varying road and load conditions, and for the characteristics of the braking mechanism which applies braking force to the wheel.

United States Patent 1191 Fleagle [76] Inventor: Joseph E. Fleagle,10907 Midland [57] ABSTRACT Ridge, Overland, Mo. 63114 A control systemfor varying the pressure applied to 1 Flledi fi 1973 fluid-controlledbrake actuating mechanisms upon de- 21 A L N I: tection of both a wheeldecelerat1on 1n excess of a pre- 1 pp 0 915 A determined threshold and asubsequent incremental Related U Appl n Data decrease in wheel velocitygreater than a continuous- [62] Division of Ser. No. 233,579, March 10,1972, ly-varying reference increment Av of wheel speed. This referenceincrement A v is inversely related to a [52] US. Cl 328/115, 307/229,328/114, variable reference signal which is directly related to 328/127,328/132, 328/146, 328/150 the rate of change of wheel speed. Thus, thecontinu- [51] llnt. Cl. H03k 5/20 o ly-varying reference increment ofwheel speed A v [58] Field of Search 307/229, 235, 261, 263; isinversely related to the rate of change of wheel 328/ 1 14-1 17, 127,146, 132, 147, 150 speed. Consequently, the period of time betweenoccurrence of a wheel deceleration in excess of said pre- [56]References Cited determined threshold and the relief of brake line fluidUNITED STATES PATENTS pressure is shorter when wheel speed decreases rap3 m7 145 H1962 Yarber 244m idly and longer when wheel speed decreasesslowly. l907O H1964 Se Compensation is thus made for varying road andload 1 ger 28/114 3,546,601 12 1970 H1111 328/116 conditions, forcharaclensncs, of the braking 3,556,610 11197-1 Leiber ..-...303/21mechamsm whlch pp braklng force to lhewheel- 3,617,904 111971 M ..3 ll7I 28/ 11 Claims, 3 Drawing Figures L I g m 576N144 mu. 0 E,

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SIG-N44 f VEPITUP mrvlk 36 MR/FIFE ATM/6 /k(l//r FROM iggggb M45712rmwozm f6 CIRCUIT WHEEL SPEED SIGNAL PROCESSING CIRCUIT FOR WHEEL SLIPCONTROL SYSTEMS Primary EraminerStanley D. Miller, Jr. Attorney, Agent,or FirmEyre, Mann & Lucas Oct. 8, 1974 PATENTLL 9 U4 SHEU 10F 3 WHEELSPEED SIGNAL PROCESSING CIRCUIT FOR WHEEL SLIP CONTROL SYSTEMSCROSS-REFERENCE TO RELATED APPLICATIONS This application is a divisionof application Ser. No. 233,579 entitled WHEEL SLIP CONTROL SYSTEM FORAUTOMOTIVE VEHICLES AND THE LIKE filed on Mar. 10, 1972 in the name ofJoseph E. Fleagle.

The system disclosed herein advantageously incorporates the brake fluidpressure modulator disclosed and claimed in application Ser. No.199,431, now US. Pat. No. 3,752,536 issued on'Aug. 14, 1973, andentitled Anti-Skid Mechanism and filed on Nov. 17, 1971 in the name ofJohn A, Machek.

BACKGROUND OF THE INVENTION The purpose of the present invention maybest be understood with the aid of a brief explanation of the prob- Ilem which is sought to be overcome. A vehicle s braking system iscapable of effecting three different relationships of wheel rotationspeed, i.e., the angular velocity of the wheel, to vehicle linear speed.These relationships are: (1) wheel rotation speed synchronized tovehicle linear speed percent wheel slip), i.e., no relative motionbetween road surface and the portion of the wheel-mounted tire which isin contact with the road surface; (2) wheel rotation speed belowsynchronization with vehicle linear speed, a condition commonly referredto as wheel slip and quantified-by the formula Synchronous Wheel SpeedActual Wheel Speed/Synchronous Wheel Speed X 100 percent Wheel Slip;

and (3) wheel not rotating while vehicle is in motion, a conditioncommonly referred to as wheel skid (100 percent wheel slip). Any driver,by pressing on the brake pedal, can easily produce the first and last ofthese relationships. It is the second relationship, the wheel rotatingbelow synchronization speed, that is very difficult to obtain even by avery experienced test driver. Road friction variations, vehicle loadingand brake sensitivity and stability are several of the major reasons whythis state is so difficult to obtain. Therefore, most drivers brake insuch a manner that the vehicle wheels are either synchronized to vehiclespeed or completely locked. Both of these situations may result in astraight-line stop, but there are exceptions. Generally, braked wheelsthat are synchronously rotating throughout the entire stop will givestraight-line stops. Theoretically, locked wheels should also givestraightline stops, but frequently do not in actual practice becausebrakes do not always lock up at the same time. The small initial angularimpulse resulting from nonsimultaneous lock-up starts the vehiclerotating as it slides. As the center of gravity shifts further andfurther off center, inertial forces continue to rotate the vehicle. Arotational deviation of approximately between the vehicle center lineand vehicle direction vector makes it almost impossible to regaincontrol. Therefore, maximum controllability can only be achieved withrolling wheels.

It has long been known that a rubber tire has maximum tractive force orgrip on the road when it is pushed beyond the state of simple statictraction, but

not so far as to lose all its gearing with the road surface. This rangeof maximum traction occurs when the tire angular speed is below thecorresponding linear speed of the vehicle, i.e., when there is somedegree of wheel slip. As was pointed out earlier, wheel slip is the mostdifficult condition to attain. Recent information has also pointed outthat impending skid stops on high friction surfaces do not shorten thestopping distance as much as on a low friction surface. On mostsurfaces, however, it has been found that maximum tractive forces occurwhen the tire angular speed is at least 10 percent lower than theangular speed at which the tire would be in synchronization with thelinear vehicle speed. Therefore, on any given road surface, the shorteststop possible can only be made if this wheel slip condition is met. Thepurpose of the present invention is to achieve this condition byactuating a brake line pressure modulator after the angular decelerationof a braked wheel reaches a predetermined minimum value and wheel speedsubsequently decreases by more than a continously-varying referenceincrement.

SUMMARY OF THE INVENTION The present invention is embodied in andcarried out by a wheel-slip control system and various subcombinationsthereof, said system being operative to vary brake line pressure toachieve a desirable percentage of wheel-slip under widely varyingconditions of vehicle load weight distribution and varying tire-roadinterface conditions. This high degree of adaptivity of applicantswheel-slip control system derives from applicants novel utilization ofsignals proportional to wheel velocity and rate of change of wheelvelocity to determine when brake line pressure is to be reduced. Morespecifically, the decrease of the velocity of a selected wheel from thetime a predetermined deceleration threshold has been exceeded by thatwheel is monitored to determine if a predetermined increment Av has beenexceeded, at which time a sharp reduction in brake line fluid pressureis effected. The increment of wheel speed Av is defined by the value ofwheel speed at the time said deceleration threshold is exceeded and areference signal which varies continuously and in direct relationship tothe rate of change of wheel speed.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention may be betterunderstood by reading the written description thereof with reference tothe accompanying drawings, of which:

FIG. 1 is a block diagram of the preferred embodi ment of applicantswheel-slip control system;

FIG. 2 is a schematic wiring diagram of the signal processing circuitryincluded in the block diagram of FIG. 1; and

FIG. 3comprises a series of graphs representative of values of severalsignificant parameters during two different cycles of the wheel-slipcontrol system illustrated in FIGS. 1 and 2, all of said graphs having acommon time base. 1

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring specificallyto the block diagram shown in FIG. 1, first and second wheel speedsignals are generated, the first by hall-effect sensor 10 connected to afirst wheel so as to generate a continuous train of pulses varying infrequency in direct proportion to wheel speed. This pulse train is fedinto a one-shot multivibrator 12, which in turn generates avariablefrequency train of pulses of constant amplitude and width. Thistrain of standardized pulses is converted to a first wheel speed analogsignal by filter 14. In like manner, a second wheel speed analog signalis gener ated by hall-effect sensor 16, one-shot multi-vibrator 18, andfilter circuit 20. These wheel speed analog signals may be generated byvarious other means which are known or may become known in the art. Eachof these wheel speed analog signals is fed into wheel speed selectorcircuit 22 which operates to select the signal representative of thelowest wheel speed for transmission through filter 24 to bufferamplifier 26. Although different selection criteria may be applied, thisapproach has been found to afford optimum results, particularly in termsof vehicle stability. Thus, a signal v(t) which is proportional to thespeed of the slowestrotating wheel is provided at the output of bufferamplifier 26. This signal is fed into the low speed cutout circuit 28,which passes the signal v(t) to linear differentiator 30 as long as thesignal has a value representative of a wheel speed in excess of apredetermined minimum wheel speed (preferably mph). The purpose of thisfeature is to prevent circuit noise, such as that present in the wheelspeed signal v(t) at low speeds, from causing deceleration thresholdcircuit 32 to generate a spurious output pulse. Differentiator in turngenerates a signal a(z) proportional to the rate of change of the wheelspeed signal v(t). The rate-of-change signal a(t) forms the variableinput to deceleration threshold circuit 32, which compares a(t) to adeceleration reference signal which represents a predetermined value ofwheel deceleration (preferably 1 g). When the rate-ofchange signal a (t)exceeds the reference signal, a variable-width pulse is generated bythreshold circuit 32. This pulse is fed to one input channel of OR gate34, which in turn provides a gating pulse to gating circuit 36. Althoughthe wheel speed analog signal v(t) is continuously' fedto gating circuit36, this signal will not be passed through to velocity threshold circuit38 unless a gating pulse is provided to gating circuit 36 by OR gate 34.Once gating circuit 36 is actuated, the wheel speed signal v(t) ispassed to velocity threshold circuit 38, which then monitors thedecrease in v(t) from the initial value V of v(t) at the time gatingcircuit 36 is actuated. Thus, the initial value V is representative ofthe speed of the selected wheel at the time the deceleration thresholdof circuit 32 was reached. As v(t) decreases due to the application ofbraking force to the wheel, velocity threshold circuit 38 compares thedif ference between the initial value V and the wheel speed analogsignal v(t) with a variable reference increment of wheel velocity Av.This increment Av is defined by the difference between the initial valueV,, which is fixed in any given cycle but varies from cycle to cycle,and the instantaneous value of the output of reference signal generator40, which increases or decreases as the rate-of-change signal a(t)increases or decreases, respectively. The net effect is to provide acontinuouslyvariable reference increment of wheel velocity Av which isinversely related to the rate-of-change signal (1(1). Thus, the morerapidly the monitored wheel decelerates upon initial braking, the soonervelocity threshold circuit 38 will produce a variable-width slip pulsewhich will be fed to OR gate 84. In response to this slip pulse, OR gate42 initiates generation of a solenoid-controlling output pulse which isamplified by power amplifier 44. This output energizes the solenoid 46which in turn actuates the brake fluid pressure modulator 48. Thus, atthis point in the operating cycle, brake line fluid pressure isrelieved. The rate-of-change signal a(l) consequently decreases from itsdeceleration threshold-exceeding value, thereby terminating the outputpulse of deceleration threshold circuit 32.

The timer 50 is also actuated by the initiation of the variable-widthslip pulse generated by velocity threshold circuit 38. For apredetermined period of time measured from such actuation, preferablyabout 0.16 second, timer 50 provides a logic 1 input to OR gate 34 sothat gating circuit 36 will remain actuated after termination of thevariable width pulse generated by deceler ation threshold circuit 32, inthe event the termination of that pulse occurs before the output oftimer 50 terminates. Thus, comparison of the velocity signal v(t) withthe initial value V of that signal can continue after the decelerationof the selected wheel falls below the reference threshold of circuit 32.The output pulse of velocity threshold circuit 38 can be terminated byeither (1) wheel spin-up beyond the threshold value determined byreference signal generator and initial wheel speed value V or (2)termination of the output of timer 50. For the same predetermined periodof time, the timer provides a logic 0 input to AND gate 52 in order todisable it from generating an output. The reasons for this operationalfeature will become apparent further on in this description.

As the selected wheel speed increases, the output pulse of velocitythreshold circuit 38 will terminate when wheel speed analog signal v(t)reaches a value at which the difference between it and the initial valueV is less than the now-increasing reference increment Av resulting fromthe decreasing output of variable reference signal generator40. Aspointed out earlier, the

magnitude of this reference increment Av is inversely related to themagnitude of the rate-of-change signal a(t). Upon termination of theoutput pulse of velocity threshold circuit 38, the solenoid-controllingoutput pulse of OR gate 42 is terminated, resulting in deenergization ofthe solenoid 46. This completes one typical cycle of the signalprocessing circuit. As this cycle is repeated, decreasing initial valuesV V V,, of the decreasing wheel speed analog signal v(t) are employed incombination with the continuouslyvarying output of reference signalgenerator 40 to define Av within each cycle.

Under certain conditions, e.g., on a low-friction sur-' face, it ispossible for the monitored wheel to develop a considerable degree ofslip before it reaches the predetermined deceleration threshold.Consequently, the decrease in wheel speed measured from the time thedeceleration threshold is exceeded is not truly representative of wheelslip, since the measurement has begun late. Also, it may happen that themonitored wheel decelerates so sharply that due to electronic processinglags, the sample V, is not a good approximation of synchronous wheelspeed. The result in both of these cases is that the wheel locks upbecause brake fluid line pressure is not relieved either fast enough orlong enough. To overcome such problem situations, the signal processingcircuit includes means for providing an input to OR gate 42 whenever theoutput of velocity threshold circuit 38 has a duration longer than thepredetermined period of time during which timer 50 gencratcs its outputsafter actuation by the leading edge of the variable-width slip pulse.Specifically, OR gate 52, AND gate 52 and acceleration threshold circuit54 operate to extend the period of relief of brake fluid line pressureunder the aforementioned conditions. If the monitored wheel has notaccelerated to a speed which will cause termination of thevariable-width slip pulse generated by velocity threshold circuit 38 atthe time the timer 50 returns to its normal condition and provides alogic 0 input to OR gate 34 and a logic 1 input to AND gate 52, then ANDgate 52 can be enabled by an output from acceleration threshold circuit54. The acceleration reference signal fed into threshold circuit 54 isrepresentative of a predetermined value of wheel acceleration(preferably +2g). Since brake fluid line pressure is still at zero whentimer 50 returns to its normal condition, the wheel must be acceleratingtoward synchronous velocity at that time. If such acceleration isgreater than the acceleration reference signal fed into thresholdcircuit 54 when the slip pulse output of velocity threshold circuit 38terminates, then logic 1 inputs willcoincidentally be fed to each of thethree input channels of AND gate 52, which will in turn generate a logic1 output. Thus, the output of OR gate 42 is continued, withoutinterruption, by the application of this input from AND gate 52 to oneinput channel just before the input formed by the slip pulse generatedby velocity threshold circuit 38 is removed from the other inputchannel. As a result, solenoid 46 remains energized until theacceleration of the monitored wheel falls below the value represented bythe acceleration reference signal fed into threshold circuit 54L By thusextending the period of time in which brake fluid line pressure is atzero, it is assured that the monitored wheel will spin-up close tosynchronous velocity.

From the foregoing description, it will be readily apparent that theoutput generated by AND gate 52 must be applied to one input channel ofOR gate 42 before the slip pulse output of velocity threshold circuit 38is removed from the other input channel of OR gate 42. Operation of thecircuit in this manner is ensured by the fact that the cumulative delaytime through the timer 50, the OR gate 34, the gating circuit 36 and thevelocity threshold circuit 38 is significantly longer than thecumulative delay time through OR gate 42 and AND gate 52. Thus, AND gate52 will always be able to provide a parallel input to one channel of ORgate 42 before the termination of the slip pulse input to the otherchannel of OR gate 42. Therefore, a race condition is never developed inthe'output-pulse-extending circuitry.

Referring now specifically to the schematic wiring diagram of FIG. 2,this represents a preferred form of r the signal processing circuitry inthe system shown in FIG. 1. It will be readily apparent that there is adirect correlation between the sub-circuits in this figure, and thesub'circuits shown in block form in FIG. 11, and the same referencenumerals are employed in both figures to facilitate such correlation. Inthe preferred embodiment of the signal processing circuitry shown inFIG. 2, the values and/or part numbers of the various circuit componentsare as follows:

Resistances Capacitances R19 6.8K ohms C11 l microfarad, C12 1microlarad -Continued R21 6.8K ohms C13 I microfarad R22 680 ohms C14100 picofarads R23 1K ohm C l microfurad R24 15K ohms C16 .047microfarad R25 4.7K ohms C17 100 picofarads R26 430K ohms C18 .047microfarad R27 1K ohm C19 1 microfarad R28 33K ohms R29 12K ohms R302.2K ohms Diodes R31 33K ohms D5 IN914 R32 -15K ohms D6 -1N9l4 R33 3.9Kohms D7 1N914 R34-33K ohms D8 -1N914 R35 10K ohms D9 1N914 R36100ohmsD10 1N914 R37-1K0hm D11-1N914 R38-12Kohms D12-1N914 R39 1Kohm D13-1N4754R40 22K ohms R41 360 ohm R42 6.8K ohms Transistors R43 10K ohms R44 10Kohms Q5 2N425O R45 33K ohms Q6 2N4250 R46 3.9K ohms Q7 2N3565 R47 2.2Kohms Q8 2N4250 R48 100K ohms Q9 2N4220 R49 2.2K ohms O12 2N3567 R50 -10Kohms Q13 2N3565 R51 10 ohms Q14-2N3567 R53 -10K ohms Q15 2N3565 Q17MJE2901 Integrated Circuit-s A1 AD741H A2 AD741H A3 MC1709G A4 MC 1 709GReferring now specifically to the graphs of FIG. 3, the initial cyclesillustrates the operation of applicants system when the monitored wheelis travelling over a high-friction surface, i.e., a dry road. Theinitiation of the application of brake fluid pressure (graph H) to thebrake actuating mechanism occurs at time T As brake fluid pressure risesand causes the application of increasing braking force to the wheel, thewheel decelerates and exceeds the threshold value of deceleration whichis fed into deceleration threshold-circuit-32 at time T Thus,deceleration threshold circuit 32 initiates the generation of adeceleration pulse (graph B) at time T Simultaneously, circuit 36 isactuated to pass the wheel speed signal v(t) to velocity thresholdcircuit 38 for comparison (graph C) when the variable referenceincrement of speed Av is exceeded, i.e., when the value of the voltagepin 2 of IC A1 falls below the output of the variable reference signalgenerator 40 (the voltage at pin 3 of IC All), generation of a slippulse is initiated by velocity threshold circuit 38 at time TSimultaneously, timer 50 initiates the generation of a logic 1 outputwhich is fed to OR gate 34 (graph E) and a logic 0 output of the sameduration which is fed to AND gate 52. Initiation of an actuating inputto solenoid 46 (graph G) occurs simultaneously with the initiation ofthe slip pulse (graph D). Thus, brake fluid pressure drops sharply fromtime T The resultant decrease in braking force causes wheel decelerationto fall belowthe threshold of deceleration threshold circuit 32 and thedeceleration pulse of the circuit is consequently terminated at time TAs may be seen from the wheel velocity signal (graph A), wheel velocitybeginsto increase shortly after time T As the wheel accelerates, itexceeds the threshold of acceleration threshold circuit 54, therebycausing the initiation of acceleration pulse (graph F) at time THowever, AND gate 52 remains disabled by the logic 0 input from timer 50(not shown), which input is concurrent with the logic 1 output of timerS (graph E). Thus, AND gate 52 will not generate an output. When theslip pulse (graph D) terminates at time T as a result of the wheelvelocity signal (graph A) having increased sufficiently to cause thevoltage at pin 2 of 1C Al to exceed the decreasing variable referencesignal applied to pin 3 of IC Al, the input to solenoid 46 (graph G) issimultaneously terminated. Since the output of OR gate 42 terminateswith the termination of the slip pulse, another of the necessary inputsto AND gate 52 is removed. Consequently, the output of OR gate 42 willnot be extended in this cycle by an output from AND gate 52.

With the de-energization of solenoid 46, brake fluid pressure begins torise sharply. The sudden decrease in the rate of increase of brake fluidpressure which occurs between time T and T is a result of thecharacteristic of the brake fluid pressure modulator which is preferablyemployed in applicants system and which is the subject of the copendingpatent application crossreferenced at the beginning of thisspecification. At time T the fixed period of timer 50 runs out and thelogic 1 signal fed to OR gate 34 terminates. Simultaneously, thedisabling logic 0 signal fed to AND gate 52 also terminates. As thewheel approaches synchronous velocity, its acceleration decreases to alevel which is below the threshold of acceleration threshold circuit 54.Consequently, acceleration pulse generated by that circuit (graph F)terminates at time T Thus, one typical cycle of the system has beencompleted.

The second cycle shown in FIG. 3 illustrates the operation of applicantssystem when the monitored wheel is travelling over a low-frictionsurface, i.e., an oil slick or a patch of ice on the road. With thebrake fluid pressure still increasing beyond time T the wheel will againbegin to decelerate until it exceeds the deceleration reference signalof threshold circuit 32 at time T at which time generation of adeceleration pulse is initiated (graph B). When the wheel speed signalcurve and the variable reference signal curve (graph C) again intersectat time T velocity threshold circuit 38 again initiates generation of aslip pulse (graph D), solenoid 46 is energized (graph G), and timer 50again generates a logic 1 output which is fed to OR gate 34, along witha logic 0 output which is fed to AND gate 52 to disable same. Because ofthe response time delay introduced by the inertia of the brakingmechanism and the lack of traction of the wheel on the slippery surface,wheel velocity drops sharply (graph A) even though brake fluid linepressure (graph H) is rapidly reduced after time T The wheel is verynearly locked up at time T at which time the deceleration pulse (graphB) terminates. Subsequently, wheel velocity begins to increase andcauses the initiation of an acceleration pulse (graph F) at time THowever, the slip pulse gener ated by velocity threshold circuit 38(graph D) terminates at time T as a result of the expiration of timer50. However, wheel velocity is still far below synchronous velocity atthis time. Thus, the input to solenoid 46 (graph G) is extended bygeneration of an output by AND gate 52 in response to the logic 1 inputfrom the output of OR gate 42, the logic 1 input from the accelerationthreshold circuit 54, and the logic 1 input from timer 50 which resultswhen the fixed period of time of timer 50 runs out. As previouslyexplained in connection with FIG. 1, the'cumulative time delay in theloop from the output of velocity threshold circuit 38 through timer 50,OR gate 34, gating circuit 36 and velocity threshold circuit 38 arelonger than the cumulative time delay in the loop through OR gate 42 andAND gate 52, so that a race condition will not develop at the input ofOR gate 42. So long as AND gate 52 produces an output, the input tosolenoid 46 (graph G) will be extended. During this period of time,brake fluid pressure at the brake actuating mechanism (graph H) is heldat zero level. Consequently, the wheel velocity (graph A) will increaserapidly. As synchronous wheel velocity is approached, wheel accelerationbegins to decrease and causes termination of the acceleration pulsegenerated by acceleration threshold circuit 54 at time T This removesone of the necessary inputs to AND gate 52, which results in terminationof the output of AND gate 52 and consequently of OR gate 42.

Thus, the input to solenoid 46 (graph G) is also termi-- nated at time TThe system has completed another typical cycle.

Various significant advantages are afforded by the wheel slip controlsystem just described. The rate compensation feature embodied in thevariable reference signal generator enables the system to provide a moreuniform percentage of slip from cycle to cycle for varying roadcoefficients and load values of distribution. Also, the determination ofbrake reapplication time according to wheel velocity, wheelacceleration, and the value of wheel speed at the time skid commenced ineach cycle makes the system highly adaptive to a wide range ofconditions which affect these parameters. This flexibility of thesystems response is also derived from the rate compensation feature,i.e., the provision of a continuously-variable reference signal directlyproportional to the rate of change of wheel speed to the velocitythreshold circuit to develop a variable reference increment of wheelspeed Av. Furthermore, the system has a high degree of immunity tospurious decelerations which do not result in a substantial change inwheel speed. Such decelerations may be caused by bumps in the road,peculiarities of the vehicles suspension system and flexing of thewheel-mounted tires. Such spurious decelerations cause only thegeneration of a brief deceleration pulse, which ,in and of itself cannotcause a change in braking force. Larger wheel velocity changes whichindicate a true skid cause the brake fluid pressure modulator to beactuated by the solenoid, thereby affecting sharp relief of brake fluidpressure and consequently braking force.

These and other advantages of the present invention, as well as ceetainchanges and modifications of the disclosed embodiment thereof, will bereadily apparent to those skilled in the art. For example, DC generatorshaving the proper range of output voltages could be connected to thevehicle wheels to provide a voltage which is proportional to the speedof each vehicle wheel, thus replacing the combinations of hall-effectsensor, one-shot multi-vibrator and filter in the embodiment disclosedherein. In addition, rather than select one of a plurality of wheelspeed signals as the input to the signal processing circuitry, a singlepreselected wheel assembly could be fitted with a generating device toprovide a signal directly to the buffer amplifier of applicants system,thereby obviating the need for a wheel speed selector. The disclosedembodiment could also be reduced to more basic configurations by theelimination of various component circuits. For example, the low speedcut-out could be removed and the output of the buffer fed directly tothe linear differentiator. Alternatively, the low speed cut-outdisclosed herein could be replaced by the circuitry which performs asimilar function in copending US. Pat. application Ser. No. 218,378entitled WHEEL SLIP CON- TROL SYSTEM FOR AUTOMOTIVE VEHICLES AND THELIKE filed on Jan. 17, 1972 in the name of Joseph E. Fleagle. The timer50 could be removed, with the output of velocity threshold circuit 38vbeing fed directly to OR gate 34. A more rudimentary system could alsobe formed by removing OR gate 42 and AND gate 52 and accelerationthreshold circuit 54, i.e., the means by which the input to solenoid 46is extended beyond the termination of the output of velocity thresholdcircuit 38, with the latter being directly connected to power amplifier44. Brake fluid pressure modulators other than that disclosed in thecopending patent application cross-referenced herein could beincorporated in applicants system. It is the applicants intention tocover all such changes and modifications which could be made to theembodiment of the invention herein chosen for the purposes of thedisclosure without departing from the spirit and scope of the invention.

What is claimed is:

1. A signalprocessing circuit comprising:

1. first circuit means operative to generate a first variable-widthpulse whenever the first derivative of an input signal exceeds a firstreference signal;

2. second circuit means operative to generate a second variable-widthpulse whenever said input signal falls below a second, continuouslyvariable reference signal after initiation of said first variablewidthpulse; and

3. third circuit means operative to generate a variable-width outputpulse in response to at least said second variable-width pulse.

2. The circuit according to claim 1 wherein said second, continuouslyvariable reference signal is directly related to said first derivativeof said input signal.

3. The circuit according to claim 1 wherein said first circuit meanscomprises:

1. differentiator means operative to generate said first derivative ofsaid input signal; and

2. first threshold circuit means operative to generate vsaid firstvariable-width pulse whenever said first derivative of said input signalexceeds said first reference signal.

4. The circuit according to claim '3 wherein said second circuit meanscomprises:

1. gating circuit means operative in response to at least said firstvariable-width pulse to pass said input signal to 2. second thresholdcircuit means operative to compare said input signal to said second,continuously variable reference signal and to generate said secondvariable-width pulse whenever said input signal falls below said second,continuously variable reference signal; and

3. variable reference signal generator means operative to receive saidfirst derivative of said input signal and to generate said second,continuously varil. timer means operative in response to initiation ofsaid second variable-width pulse to generate at least a first output fora predetermined period of time after initiation of said secondvariable-width pulse; and

2. first logic means operative in response to either said firstvariable-width pulse or said first output of said timer means to causesaid gating circuit means to pass said input signal to said secondthreshold circuit means.

6. The circuit according to claim 5 wherein said third circuit meanscomprises:

1. third comparison means operative to generate a third variable-widthpulse whenever said first derivative of said input signal exceeds' athird reference signal;

. second logic means operative to generate said variable-width output inresponse to either said second variable-width pulse output from saidsecond comparison means or the output from 3. third logic meansoperative in response to the coincidence of a second output from saidtimer means,

a third variable-width pulse output from said third comparison means,and an output from said second logic means to extend the output of saidsecond logic means after termination of said second variable-width pulseoutput from said second comparison means.

7. The circuit according to claim 6 wherein said second logic meanscomprises an OR gate, and said third logic means comprises an AND gate.

8. The circuit according to .claim 6 wherein said third circuit meansfurther comprises power amplifier means operative to receive and amplifysaid output from said second logic means.

9. Thecircuit according to claim 1 wherein said third circuit meanscomprises:

1. third comparison means operative to. generate a third variable-widthpulse whenever said first derivative of said input signal exceeds athird reference signal;

2. timer means operative in response to initiation of said secondvariable-width to generate an output for a predetermined period of timeafter initiation of said second variable-width pulse;

3. secondlogic means operative to generate said variable-width output inresponse to either said second variable-width pulse output from saidsecond com-' parison means or the output from I third logic meansoperative in response to the coin- .cidence of said output from saidtimer means, said third variable-width pulse output from said comparisonmeans, and said variable-width output from said second logic means toextend the output of said second logic means after termination of saidsecond variable-width pulse output from said second comparison means.10. The circuit according to claim 9 wherein said second logic meanscomprises an OR gate, and said third logic means comprises an AND gate.

11. The circuit according to claim 9 wherein said third circuit meansfurther comprises power amplifier means operative to receive and amplifysaid output from said second logic means.

1. A signal-processing circuit comprising:
 1. first circuit meansoperative to generate a first variablewidth pulse whenever the firstderivative of an input signal exceeds a first reference signal; 2.second circuit means operative to generate a second variablewidth pulsewhenever said input signal falls below a second, continuously variablereference signal after initiation of said first variable-width pulse;and
 3. third circuit means operative to generate a variable-width outputpulse in response to at least said second variable-width pulse. 2.second circuit means operative to generate a second variable-width pulsewhenever said input signal falls below a second, continuously variablereference signal after initiation of said first variable-width pulse;and
 2. first threshold circuit means operative to generate said firstvariable-width pulse whenever said first derivative of said input signalexceeds said first reference signal.
 2. The circuit according to claim 1wHerein said second, continuously variable reference signal is directlyrelated to said first derivative of said input signal.
 2. timer meansoperative in response to initiation of said second variable-width togenerate an output for a predetermined period of time after initiationof said second variable-width pulse;
 2. second logic means operative togenerate said variable-width output in response to either said secondvariable-width pulse output from said second comparison means or theoutput from
 2. first logic means operative in response to either saidfirst variable-width pulse or said first output of said timer means tocause said gating circuit means to pass said input signal to said secondthreshold circuit means.
 2. second threshold circuit means operative tocompare said input signal to said second, continuously variablereference signal and to generate said second variable-width pulsewhenever said input signal falls below said second, continuouslyvariable reference signal; and
 3. third logic means operative inresponse to the coincidence of a second output from said timer means, athird variable-width pulse output from said third comparison means, andan output from said second logic means to extend the output of saidsecond logic means after termination of said second variable-width pulseoutput from said second comparison means.
 3. variable reference signalgenerator means operative to receive said first derivative of said inputsignal and to generate said second, continuously variable referencesignal.
 3. second logic means operative to generate said variable-widthoutput in response to either said second variable-width pulse outputfrom said second comparison means or the output from
 3. third circuitmeans operative to generate a variable-width output pulse in response toat least said second variable-width pulse.
 3. The circuit according toclaim 1 wherein said first circuit means comprises:
 4. third logic meansoperative in response to the coincidence of said output from said timermeans, said third variable-width pulse output from said comparisonmeans, and said variable-width output from said second logic means toextend the output of said second logic means after termination of saidsecond variable-width pulse output from said second comparison means. 4.The circuit according to claim 3 wherein said second circuit meanscomprises:
 5. The circuit according to claim 4 wherein said secondcircuit means further comprises:
 6. The circuit according to claim 5wherein said third circuit means comprises:
 7. The circuit according toclaim 6 wherein said second logic means comprises an OR gate, and saidthird logic means comprises an AND gate.
 8. The circuit according toclaim 6 wherein said third circuit means further comprises poweramplifier means operative to receive and amplify said output from saidsecond logic means.
 9. The circuit according to claim 1 wherein saidthird circuit means comprises:
 10. The circuit according to claim 9wherein said second logic means comprises an OR gate, and said Thirdlogic means comprises an AND gate.
 11. The circuit according to claim 9wherein said third circuit means further comprises power amplifier meansoperative to receive and amplify said output from said second logicmeans.